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A few years ago, multiple high-end companies were bankroll the idea of moving from 300mm to 450mm silicon wafers. Historically, moving to larger wafers was a critical way that foundries and fabs cut prices and improved yields. Historically, companies like Intel led the accuse on wafer size, but there's ever been a very long tail. Currently, some 23 firms have 300mm fabs in production, while 58 companies nevertheless operate 200mm fabs. 450mm wafers were meant to further extend the cost savings of 300mm wafers, but high costs and uncertain rollouts announced to have doomed the effort.

Several years ago, Intel, Samsung, GlobalFoundries, TSMC, and IBM collectively launched the Global 450 Consortium (G450C) in partnership with The Colleges of Nanoscale Science and Engineering science (CNSE) at SUNY Polytechnic Institute (SUNY Poly). This collaboration was a $4.8 billion-dollar endeavor (over five years) to develop tools, work with suppliers on 450mm ecosystem evolution, and to create appropriate infrastructure for the future deployment of 450mm wafers. This was no small chore — larger wafers ways different tools, and tool costs are a substantial reason why process nodes are becoming more expensive over fourth dimension. EUV tools and lithography equipment, for case, are significantly more expensive than traditional 193nm ArF lasers. According to a recent report in the Times-Spousal relationship, two of the five companies involved in the G450C are pulling out later the end of the five-twelvemonth program.

Graph and data by ICInsights.

Graph and data by ICInsights.

A report from IC Insights published in October 2022 sheds some additional light on this situation. While 300mm wafers are more popular than 200mm wafers in terms of total product chapters, they are likewise limited to specific areas of the market place. DRAM, NAND flash, epitome sensors, power management devices, CPUs, GPUs, and other loftier book technologies are typically built on 300mm wafers. 200mm wafers are used for smaller runs, where lower full volumes are expected. We've discussed before how TSMC makes a meaning percent of its income using nodes that haven't been cutting-edge in a decade or more. Many of these older nodes are paired with older equipment to continue them toll-constructive and minimize the purchase of new hardware.

450mm-wafercosts

Intel's estimated wafer costs, when information technology nevertheless expected 450mm wafers to exist A Affair.

At that place are several intrinsic advantages to using larger wafers. If the foundry can keep its wafers-per-hour production rate on 450mm wafers close to its 300mm wafer production rate, it can produce vastly more fries per hour. This helps reduce costs, provided that the semiconductor economic system is healthy and the foundry utilization rate is high. Beingness able to build more than chips per hour can also allow older lines to be close down, saving on factory costs. Larger wafers mean that large-dice processors don't cost as much area around the edges of the wafer and reduce overall waste as a result. The graph above shows Intel's estimated wafer costs over time, and illustrates why the visitor was anxious to move to 450mm wafers over the long term. If the shift had been successful, Intel'due south long-term roadmap for Atom processors might have taken a dissimilar path, since 450mm wafers would have immune the visitor to reduce its per-die Cantlet cost and probable compete more effectively against TSMC, Samsung, and GlobalFoundries (at to the lowest degree, until those firms rolled their own 450mm wafers).

With multiple companies pulling out of G450C and no clear roadmap for the technology, information technology seems rubber to conclude that 450mm wafers are pretty much expressionless. Airplane pilot programs have ended, firms are nevertheless focused on ramping up 300mm wafers at various foundries, and no semiconductor business firm we're aware of is even so championing 450mm wafer research or deployment. Loftier costs and motorcar replacements appear to have nuked any argument for superior cost savings in the long term or improving wafer utilization.